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AS4C16M16MD1-6BCN
The 256 Mb mobile DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM.
Description
This AS4C16M16MD1 is 268,435,456 bits synchronous double data rate Dynamic RAM. Each 67,108,864 bits bank is organized as 8,192 rows by 512 columns by 16 bits, fabricated with Alliance Memory's high performance CMOS technology. This device uses a double data rate architecture to achieve high- speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.
Features
- AS4C16M16MD1
- VDD/VDDQ = 1.7~1.95V
- Data width: x16
- Clock rate: 200MHz,166MHz , 133MHz
- Partial Array Self-Refresh(PASR)
- Auto Temperature Compensated Self-Refresh(ATCSR)
- Power Down Mode
- Deep Power Down Mode (DPD Mode)
- Programmable output buffer driver strength
- Four internal banks for concurrent operation
- Data mask (DM) for write data
- Clock Stop capability during idle periods
- Auto Pre-charge option for each burst access
- Double data rate for data output
- Differential clock inputs (CK and CK )
- Bidirectional, data strobe (DQS)
- CAS Latency: 2 and 3
- Burst Length: 2, 4, 8 and 16
- Burst Type: Sequential or Interleave
- 64 ms Refresh period
- Interface: LVCMOS
- Operating Temperature Range
- Extended (-30℃ to + 85 ℃)