TechVault
GW2A-18
Description
The GW2A series of FPGA products are the first generation products of the Arora family. They offer a range of comprehensive features and rich internal resources like high-performance DSP resources, a high-speed LVDS interface, and abundant BSRAM memory resources. These embedded resources combine a streamlined FPGA architecture with a 55nm process to make the GW2A series of FPGA products suitable for high-speed, low-cost applications.
GOWINSEMI continually invests the development of next-generation FPGA hardware environment through the market-oriented independent research and developments that supports the GW2A series of FPGA products, which can be used for FPGA synthesizing, layout, place and routing, data bitstream generation and download, etc.
Features
- Lower power consumption
- 55nm SRAM technology
- Core voltage: 1.0V
- Clock dynamically turns on and off
- Multiple I/O standards
- LVCMOS33/25/18/15/12;LVTTL33,SSTL33/25/18 I, II, SSTL15; HSTL18 I, II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE MLVDSE, LVPECLE, RSDSE
- Input hysteresis option
- Supports 4mA,8mA,16mA,24mA,etc. drive options
- Slew rate option
- Output drive strength option
- Individual bus keeper, weak pull-up, weak pull-down, and open drain option
- Hot socket
- High performance DSP
- High performance digital signal processing ability
- Supports 9 x 9,18 x 18,36 x 36 bits multiplier and 54 bits accumulator;
- Multipliers cascading
- Registers pipeline and bypass 2 General Description 2.2 Product Resources DS102 -2.2E 5(52)
- Adaptive filtering through signal feedback
- Supports barrel shifter
- Abundant slices
- Four input LUT (LUT4)
- Double-edge flip-flops
- Supports shift register and distributed register
- Block SRAM with multiple modes
- Supports dual port, single port, and semi-dual port
- Supports bytes write enable
- Flexible PLLs
- Frequency adjustment (multiply and division) and phase adjustment
- Supports global clock
- Configuration
- JTAG configuration
- Four GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT
- Data stream file encryption and security bit settings
Specifications
LUT4 | 20,736 |
Flip-Flop | (FF) 15,552 |
Shadow SRAM S-SRAM (bits) | 41,472 |
Block SRAM B-SRAM (bits) | 828K |
B-SRAM quantity B-SRAM | 46 |
18 x 18 Multiplier | 48 |
Maximum1 (PLLs) | 4 |
Total number of I/O banks | 8 |
Max. I/O | 384 |
Core voltage | 1.0V |