TechVault
GW1N-1
Description
The GW1N series of FPGA products are the first generation products in the LittleBee® family. They offer abundant logic resources, multiple I/O standards, embedded BSRAM, DSP, PLL, and built-in Flash. They are non-volatile FPGA products with low power, instant-start, low-cost, highsecurity, small size, various packages, and flexible usage.
GOWINSEMI provides a new generation of FPGA hardware development environment through market-oriented independent research and development that supports the GW1N series of FPGA products and applies to FPGA synthesizing, placement and routing, data bitstream generation and download, etc.
Features
- User Flash (GW1N-1, GW1N-1S)
- 100,000 write cycles
- Greater than10 years data retention at +85℃
- Selectable 8/16/32 bits data-in and data-out
- Page size: 256 bytes
- 3 μA standby current
- Page write time: 8.2 ms
- Lower power consumption
- 55 nm embedded flash technology
- LV [1]: Supports 1.2 V core voltage
- UV: Supports unique power supply for VCC/ VCCO/ VCCx
- Note! [1] GW1N-1S supports LV Version only.
- Clock dynamically turns on and off
- Hard Core - MIPI D-PHY RX (GW1N-2)
- Interfaces to MIPI DSI and MIPI CSI-2, RX devices
- IO Bank6 in CS42, CS42H, QN48H, QN88, and MG132H packages supports MIPI D-PHY RX
- MIPI transmission rate up to 2Gbps per lane, 8Gbps per D-PHY interface;
- Supports up to 4 data lanes and one clock lane
- Multi-function Highspeed FPGA IO - MIPI D-PHY RX/TX (GW1N-2)
- Interfaces to MIPI CSI-2 and MIPI DSI, RX and TX devices
- MIPI transmission rate up to 1.5Gbps per lane, 6Gbps per port;
- MIPI D-PHY TX with dynamic ODT supported on IO Bank0, IO Bank3, IO Bank4, and IO Bank5 support
- MIPI D-PHY RX with dynamic ODT supported on IO Bank2
- Multiple I/O Standards
- LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE MLVDSE, LVPECLE, RSDSE
- Input hysteresis option
- Supports 4mA,8mA,16mA,24mA, etc. drive options
- Slew rate option
- Output drive strength option
- Individual bus keeper, weak pull-up, weak pull-down, and open drain option
- Hot socket
- BANK0/BANK1 of GW1N-1S support MIPI I/O input, and MIPI transmission speed can be up to 1.2Gbps
- I/Os in the Top layer of GW1N-9 devices support MIPI input, and MIPI transmission speed can be up to 1.2Gbps
- I/Os in the Bottom layer of GW1N-9 devices support MIPI output, and MIPI transmission speed can be up to 1.2Gbps
- I/Os in the Top layer and Bottom layer of GW1N-9 devices support I3C OpenDrain/PushPull conversion
- High performance DSP(GW1N-4/9)
- High performance digital signal processing ability
- Supports 9 x 9,18 x 18,36 x 36 bits multiplier and 54 bits accumulator;
- Multipliers cascading
- Registers pipeline and bypass
- Adaptive filtering through signal feedback
- Supports barrel shifter
- Abundant slices
- Four input LUT (LUT4)
- Supports shift register and distributed register
- Block SRAM with multiple modes
- Supports dual port, single port, and semi-dual port
- Supports bytes write enable
- Flexible PLLs
- Frequency adjustment (multiply and division) and phase adjustment
- Supports global clock
- Built-in flash programming
- Instant-on
- Supports security bit operation
- Supports AUTO BOOT and DUAL BOOT
- Configuration
- JTAG configuration
- Supports background update
- Offers up to seven GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT, I2C Slave
Specifications
LUT4 | 1,152 |
Flip-Flop (FF) | 864 |
Shadow SRAM Capacity(bits) | 0 |
Block SRAM Capacity(bits) | 72K |
Number of BSRAM | 4 |
User Flash (bits) | 96K |
18 x18 multiplier | 0 |
PLLs | 1 |
Total Number of I/O Banks | 4 |
Max. I/O | 120 |
Core Voltage (LV) | 1.2V |
Core Voltage(UV) | 1.8V-3.3V |